How to Formalize FPGA Hardware Design

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Authors	HOLEČEK Jan KRATOCHVÍLA Tomáš ŘEHÁK Vojtěch ŠAFRÁNEK David ŠIMEČEK Pavel
Year of publication	2004
Type	R&D Presentation
MU Faculty or unit	Faculty of Informatics
Citation
Description	In this report, a formal view of an FPGA hardware design is presented. An approach of how elementary FPGA design entities can be modeled in terms of Kripke structures is presented here. The report is also focused on capturing the problems of modeling synchronous parts of hardware design together with its asynchronous parts.
Related projects:	Automated Verification of Parallel and Distributed Systems Non-sequential Models of Computing -- Quantum and Concurrent Distributed Models of Computing