Packet Filtering for FPGA-Based Routing Accelerator
| Authors | |
|---|---|
| Year of publication | 2006 |
| Type | Article in Proceedings |
| Conference | CESNET Conference 2006 Proceedings |
| MU Faculty or unit | |
| Citation | |
| Web | http://www.ces.net/conference06/ |
| Field | Computer hardware and software |
| Keywords | packet filtering; hardware accelerated routing; filtring rules transformation; filtering decision diagram; binary decision diagram |
| Description | In this paper, we present a novel approach for Binary Decision Diagram based semantically extended representation of packet filters called Filter Decision Diagrams (FDD), used for efficient filter processing and lookup in a hardware accelerator that uses a lookup engine employing CAM and comparison instructions kept in SRAM. We present the most important operations for FDDs and also give some complexity estimate. We also analyze and compare expressing power of the most commonly available packet filters. |
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